37C3 - Open CPU / SoC design, all the way up to Debian

Discover the freedom to design your own CPUs and SOCs using open-source tools and RISC-V, a specification for CPU design, learn about branch prediction, cache latency, and more.

Key takeaways

Open CPU/SOC design with full Debian desktop environment
Using RISC-V CPU with Boom and Nexus 5 projects
FPGAs are simulation devices, not just for deployment
Branch prediction is a challenge in CPU design
Lockstep simulation of CPU is important
Tools like Verilator and ModelSim can be helpful for CPU design
Open-source alternatives to industry tools like VHDL and Verilog
Linux and Debian can run on FPGAs with some hardware adaptation *Perfil running devices, such as peripherals, must be included in the design
Futura is a VHDL-based language for hardware design not being implemented, and compared to Boom.
the accuracy of jump instructions is dependent on the fetch unit
Hardware cache latency can impact performance.
The CPU execution path can be corrected by correcting branch predictions
CPU keep performance low due to incorrect branch prediction.
RISC-V is a specification for CPU design and many companies use it in their silicon.
RISC-V has many extensions for integer, multiply, divide, atomic and floating point.
The accuracy of jump instructions and branch prediction is dependent on the fetch unit
SATA and PCIe are supported on some FPGAs but not on all.
Additional hardware requirements are needed to implement debug interface.
The RISC-V Linux port includes support for peripherals such as keyboard, mouse, audio and UART.
There are some cases where hardware cache latency can impact performance.
Open-source tools like Lytex can be used for hardware design.
With RISC-V, you can manually predict where jumps and branches should go.
Compressed instruction set and some modification on how they are processed
Instruction set architecture with compression(reordered code)
Linux encryption
Reading data from the DOM

37C3 - Open CPU / SoC design, all the way up to Debian

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